Isolation structures are necessary in a semiconductor wafer in order to isolate individual devices formed in the wafer. Several different isolation technologies have been proposed, including LOCOS (LOCal Oxidation of Silicon), shallow trench isolation (STI), LOCOS-based isolation such as poly-buffered LOCOS (PBL), and framed-mask PBL technologies. In that technique, isolation structures are created by thermally growing a thick field oxide layer over certain areas defined by a silicon nitride mask. Then, the silicon nitride mask is stripped.
As device geometry has shrunk to the sub-half micron order, conventional LOCOS isolation cannot meet the requirements of ULSI fabrication. The major drawback of LOCOS is the "bird's beak" effect. In this effect, the oxidant laterally diffuses at the edges of the silicon nitride during the formation of the isolation. Oxide forms under the nitride edges and lifts the nitride edges. This lateral extension of the field oxide causes unacceptably large encroachment on the field oxide into the device active regions. Further, the planarity of the surface topography is inadequate for sub-micron lithography needs.
Therefore, trench isolation offers potentially great advantages over LOCOS. Hence, STI can be considered as a replacement for conventional LOCOS isolation. Further, STI is gaining popularity for quarter-micron technology. In the basic STI technology, shallow trenches are formed in the silicon substrate by etching. Next, a gap filling material is refilled into the trenches and is then planarized by CMP (Chemical Mechanical Polishing) or etching back.
A variety of issues are generated during the development of this technology. For example, the dishing effect is one of the major issues. The dishing effect adversely impacts the planarity of a layer and impacts the control of lithography and ion implantation. The dishing effect is caused by chemical mechanical polishing that exhibits pattern-dependent polishing uniformity and instability of polishing rate.
One prior art approach to this issue is by the use of a dummy pattern. The use of this conventional method can improve the result of the CMP planarization. However, as seen in FIG. 1, the completed trench isolations 3 in the wafer 1 have shoulder recessed portions 5 formed at the edges of the structure. The shoulder recessed portions 5 will give rise to abnormal electrical characteristics in the devices. Therefore, what is required is a method of forming a trench isolation without shoulder recessed portions.